As communication technologies evolve, data transfer speeds increase along with the amount of data being transferred. These parameters continually push the data communication industry and the communication devices for providing circuits of ever increasing data handling capability.
At the same time, the semiconductor industry strives for producing integrated circuits of greater density and smaller size. These two considerations—i.e., the demand for increased data handling capability and the push for greater levels of integration—together may be understood to increase the premium for signal interfacing within the limited pin counts available across a given area of a semiconductor device.
To assist some of these demands, some manufacturers of high-speed data communication devices have developed transceivers with parallel-to-serial and serial-to-parallel data multiplexing/de-multiplexing circuit designs. By using these multiplexing circuits, the high-pin count, parallel data interfaces may be replaced with lower pin count, high-speed serial data interfaces. On a receiver side of a transceiver, for example, a high-speed serial data sequence may be received from an I/O link and then converted into parallel data of a slower clock rate. Conversely, on the transmission side of the transceiver, parallel data of a low-clock rate may be converted from the parallel format into a higher-speed, serial format.
Thus, transceivers with parallel-to-serial and serial-to-parallel multiplexing/de-multiplexing circuits may be integrated into data communication devices to enhance their data handling capability. Accordingly, these transceiver designs have found their way into various high-density, integrated circuits such as circuits for data communication devices, data processors, network modules, switchers, relays, gateways, modems, and in particular highly integrated programmable circuits, e.g., a programmable logic device (PLD) such as a Field Programmable Gate Array (FPGA).
To assist with the sampling and detection of data from a serial data input signal, a clock recovery circuit of the transceiver may determine transitions of the input data signal and control a frequency/phase of a recovered internal clock in accordance with the frequency/phase placements relative to those of the received data signal. It may be understood, however, that in order to keep the frequency/phase of the internally recovered clock in synchronous relationship to that associated with the incoming data signal, the data signal received may need to employ an encoding/decoding protocol that can assure a sufficient number of transitions over a given interval or duration for enabling appropriate closed-loop control via the transitions of the serial data signal.
Some of these encoding/decoding protocols (e.g., Ethernet, Sonet, Infiniband, Fibre Channel, etc.) may be described as a form of “non-return to zero” encoding. In a particular example, an 8 bit/10 bit (non-return to zero) protocol may encode data to assure that only a limited number (5 bits) of same-state data bits may occur consecutively within the data stream. In other words, it may assure that, e.g., only five data bits of same state (one or zero) may occur consecutively within the serial data stream. Else, absent a sufficient frequency of state transitions within the serial data signal, the clock generator of a clock recovery circuit might begin to drift or wander relative to the frequency/phase inherent within the input data signal.
Further, it may be understood that the reliability of data recovery may be dependent upon the amount of drift/wandering, or “jitter,” attributable to transceivers and their associated clock recovery circuits. Stated alternatively, the greater the performance of a given transceiver, the less wandering or drift inherent to the device, and the greater its performance and jitter tolerance thereby enabling more reliable and higher speed transfer of data. Conversely, the lower the performance and jitter tolerance of the transceiver, the lower the reliability and speed of its associated serial data transfer. Therefore, it may be understood that both the speed and reliability of a serial data communication link will depend on the jitter tolerance or performance level of the data transceivers.
Accordingly, when producing integrated circuits including programmable logic semiconductor devices, e.g., FPGA, that may comprise transceiver circuits embedded therein, which may be employed with high-speed data communication applications, it may be helpful to rate their level of performance. Further, it may be helpful to enable such rating capability in a production environment for benefit of providing classification of the components that may be produced for given data communication applications, and capable of yielding results in a short period of time.